1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having cross-point DRAM cells.
2. Description of the Related Art
In recent years, the integration density of DRAMs (Dynamic Random Access Memories) has been increased. As the integration density is increased, a capacitor area is reduced. Therefore, the contents of the memory may be erroneously read out, and data may be also broken by radiation.
In order to eliminate the above problems, capacitors having various structures have been proposed. As one of the structures, a conventional stacked capacitor cell structure is shown in FIG. 4. In FIG. 4, reference numeral 30 denotes a semiconductor substrate; 31, a field oxide film for isolation selectively formed on the substrate surface; 32, a gate oxide film formed on the substrate surface; 33, a gate electrode (word line) of a transfer-gate MOS transistor; and 34, the source/drain regions of the MOS transistor, respectively. The MOS transistor thus isolated is covered with a first insulating film 35. A first contact hole is formed in the first insulating film 35, through which a lower capacitor electrode (storage node electrode) is provided so as to be in contact with on of the source/drain regions 34 of the MOS transistor, and an upper capacitor electrode (cell plate electrode) 38 is disposed above the lower capacitor electrode 36 through an insulating film 37 to provide an MIM (metal-insulator-metal) capacitor, which includes the lower capacitor electrode 36, the insulating film 37 and the upper capacitor electrode 38. The MIM capacitor formed as described above is covered with a second insulating film 39, in which a second contact hole is formed. A bit line 40 is provided so as to be in contact with the other of the source/drain regions 34 of the MOS transistor through the second contact hole.
Although the MIM capacitor region has a three-dimensional structure, the stacked capacitor cell has a large occupied area given by the isolation region, the MOS transistor region, the bit line contact region, and spacings thereamong. Therefore, it may be difficult to provide a memory cell having hyperfine geometry structure. Even in a trench capacitor cell, the same disadvantages as described above cannot be avoided.
In Published Examined Japanese Patent Application Nos. 64-25461, 64-25462, and 64-25466, as shown in FIG. 5, a memory cell having a vertical MOS transistor structure is described. The memory cell is provided as follows. A trench 42 is formed in an N-type semiconductor substrate 40 having a P.sup.+ -type semiconductor layer 41, and a dielectric film (e.g., SiO.sub.2 film) is formed on the inner surface of the trench as an insulating film 43. Thereafter, and an N.sup.+ -type charge storage electrode 44 is provided. A word line (gate electrode) 45 and a gate oxide film 46 surrounding the periphery of the word line 45 are provided on the upper surface of the charge storage electrode 44, and a P-type semiconductor layer 47 is provided so as to bury the gate oxide film 46. An insulating film 48 is formed on the upper surfaces of the gate oxide film 46 and the p-type semiconductor layer 47. A contact hole is formed in the insulating film 48, and an N.sup.+ -type semiconductor layer 49 is deposited in the contact hole. In addition, a conductive film (e.g., polysilicon film) is deposited on the entire surface of the substrate to be in contact with the N.sup.+ -type semiconductor layer 49. Thereafter, the conductive film is patterned to provide a bit line 50.
In the memory cell that includes the trench capacitor provided in the semiconductor substrate and the MOS transistor with the vertical structure located on the trench capacitor, the planar area occupied by the MOS transistor region is decreased. Therefore, a cross-point memory cell in which a memory cell is located at the cross point of the bit line 50 and the word line 45 can be provided.
However, in the above conventional cross-point memory cell, it is difficult to obtain a sufficiently high capacitance of the capacitor as the device structure of the memory cell is reduced. That is, as a method of increasing the capacitance, it may be considered to use a dielectric film (e.g., a Ta.sub.2 O.sub.5 film or a PZT film) having a high dielectric constant as an insulating film 43. However, it is difficult to make such a film having the high dielectric constant. For example, it has been known that the properties of the film are remakably degraded by a high temperature heat treatment. On the other hand, it has been required that when the memory cell having the vertical MOS transistor structure is made, a process after forming the capacitor is performed at a low temperature. However, since the word line 45 and the bit line 50 are provided after the formation of the capacitor, it is difficult to reduce the heat treating time or to decrease the temperature of the heat treatment.